M68ICS08GR datasheet(259/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

259

DMARE — DMA Receive Enable Bit

CAUTION:

The DMA module is not included on this MCU. Writing a logic 1 to

DMARE or DMATE may adversely affect MCU performance.

1 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt

requests enabled)

0 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt

requests enabled)

DMATE — DMA Transfer Enable Bit

CAUTION:

The DMA module is not included on this MCU. Writing a logic 1 to

DMARE or DMATE may adversely affect MCU performance.

1 = SCTE DMA service requests enabled; SCTE CPU interrupt

requests disabled

0 = SCTE DMA service requests disabled; SCTE CPU interrupt

requests enabled

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

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