M68ICS08GR datasheet(256/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Technical Data

MC68HC908GR8 — Rev 4.0

256

Serial Communications Interface (SCI)

MOTOROLA

SCTIE — SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter

CPU interrupt requests. Reset clears the SCTIE bit.

1 = SCTE enabled to generate CPU interrupt

0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU

interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

SCRIE — SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver

CPU interrupt requests. Reset clears the SCRIE bit.

1 = SCRF enabled to generate CPU interrupt

0 = SCRF not enabled to generate CPU interrupt

ILIE — Idle Line Interrupt Enable Bit

This read/write bit enables the IDLE bit to generate SCI receiver CPU

interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests

0 = IDLE not enabled to generate CPU interrupt requests

TE — Transmitter Enable Bit

Setting this read/write bit begins the transmission by sending a

preamble of 10 or 11 logic 1s from the transmit shift register to the

PE2/TxD pin. If software clears the TE bit, the transmitter completes

any transmission in progress before the PE2/TxD returns to the idle

Address:

$0014

Bit 7

654321

Bit 0

Read:

SCTIE

TCIE

SCRIE

ILIE

RWU

SBK

Write:

Reset:

00000000

Figure 18-10. SCI Control Register 2 (SCC2)

Freescale Semiconductor, Inc.

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