M68ICS08GR datasheet(255/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

255

NOTE:

Changing the PTY bit in the middle of a transmission or reception can

generate a parity error.

18.9.2 SCI Control Register 2

SCI control register 2:

•

Enables the following CPU interrupt requests:

–

Enables the SCTE bit to generate transmitter CPU interrupt

requests

–

Enables the TC bit to generate transmitter CPU interrupt

requests

–

Enables the SCRF bit to generate receiver CPU interrupt

requests

–

Enables the IDLE bit to generate receiver CPU interrupt

requests

•

Enables the transmitter

•

Enables the receiver

•

Enables SCI wakeup

•

Transmits SCI break characters

Table 18-5. Character Format Selection

Control Bits

Character Format

PEN and

PTY

Start

Bits

Data

Bits

Parity

Stop

Bits

Character

Length

None

10 bits

None

11 bits

Even

10 bits

Odd

10 bits

Even

11 bits

Odd

11 bits

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