M68ICS08GR datasheet(303/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Transmission Formats

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

303

When the master SPI starts a transmission, the data in the slave shift

data register. The slave must write to its transmit data register at least

one bus cycle before the master starts the next transmission. Otherwise,

the byte already in the slave shift register shifts out on the MISO pin.

Data written to the slave shift register during a transmission remains in

a buffer until the end of the transmission.

When the clock phase bit (CPHA) is set, the first edge of SPSCK starts

a transmission. When CPHA is clear, the falling edge of SS starts a

transmission. See Transmission Formats.

NOTE:

SPSCK must be in the proper idle state before the slave is enabled to

prevent SPSCK from appearing as a clock edge.

20.6 Transmission Formats

During an SPI transmission, data is simultaneously transmitted (shifted

out serially) and received (shifted in serially). A serial clock synchronizes

shifting and sampling on the two serial data lines. A slave select line

allows selection of an individual slave SPI device; slave devices that are

not selected do not interfere with SPI bus activities. On a master SPI

device, the slave select line can optionally be used to indicate multiple-

master bus contention.

20.6.1 Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SPSCK)

phase and polarity using two bits in the SPI control register (SPCR). The

clock polarity is specified by the CPOL control bit, which selects an

active high or low clock and has no significant effect on the transmission

format.

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