M68ICS08GR datasheet(305/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Transmission Formats

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

305

Figure 20-4. Transmission Format (CPHA = 0)

Figure 20-5. CPHA/SS Timing

When CPHA = 0 for a slave, the falling edge of SS indicates the

beginning of the transmission. This causes the SPI to leave its idle state

and begin driving the MISO pin with the MSB of its data. Once the

transmission begins, no new data is allowed into the shift register from

the transmit data register. Therefore, the SPI data register of the slave

must be loaded with transmit data before the falling edge of SS. Any data

written after the falling edge is stored in the transmit data register and

transferred to the shift register after the current transmission.

20.6.3 Transmission Format When CPHA = 1

Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The

figure should not be used as a replacement for data sheet parametric

information. Two waveforms are shown for SPSCK: one for CPOL = 0

and another for CPOL = 1. The diagram may be interpreted as a master

or slave timing diagram since the serial clock (SPSCK), master in/slave

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

123

SPSCK CYCLE #

FOR REFERENCE

SPSCK; CPOL = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

SS; TO SLAVE

CAPTURE STROBE

BYTE 1

BYTE 3

MISO/MOSI

BYTE 2

MASTER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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