M68ICS08GR datasheet(306/408 Pages) FREESCALE

306 / 408 page

Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

306

Serial Peripheral Interface (SPI)

MOTOROLA

out (MISO), and master out/slave in (MOSI) pins are directly connected

between the master and the slave. The MISO signal is the output from

the slave, and the MOSI signal is the output from the master. The SS line

is the slave select input to the slave. The slave SPI drives its MISO

output only when its slave select input (SS) is at logic 0, so that only the

selected slave drives to the master. The SS pin of the master is not

shown but is assumed to be inactive. The SS pin of the master must be

high or must be reconfigured as general-purpose I/O not affecting the

SPI. See Mode Fault Error. When CPHA = 1, the master begins driving

its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first

SPSCK edge as a start transmission signal. The SS pin can remain low

between transmissions. This format may be preferable in systems

having only one master and only one slave driving the MISO data line.

Figure 20-6. Transmission Format (CPHA = 1)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

123

SPSCK CYCLE #

FOR REFERENCE

SPSCK; CPOL = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

; TO SLAVE

CAPTURE STROBE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

M68ICS08GR Datasheet(PDF) 306 Page - Freescale Semiconductor, Inc

M68ICS08GR Datasheet(HTML) 306 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL