M68ICS08GR datasheet(314/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

314

Serial Peripheral Interface (SPI)

MOTOROLA

slave. This happens because SS at logic 0 indicates the start of the

transmission (MISO driven out with the value of MSB) for CPHA = 0.

When CPHA = 1, a slave can be selected and then later unselected with

no transmission occurring. Therefore, MODF does not occur since a

transmission was never begun.

In a slave SPI (MSTR = 0), the MODF bit generates an SPI

receiver/error CPU interrupt request if the ERRIE bit is set. The MODF

bit does not clear the SPE bit or reset the SPI in any way. Software can

abort the SPI transmission by clearing the SPE bit of the slave.

NOTE:

A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high

impedance state. Also, the slave SPI ignores all incoming SPSCK

clocks, even if it was already in the middle of a transmission.

To clear the MODF flag, read the SPSCR with the MODF bit set and then

write to the SPCR register. This entire clearing mechanism must occur

with no MODF condition existing or else the flag is not cleared.

20.9 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt

requests.

Table 20-2. SPI Interrupts

Flag

Request

SPTE

Transmitter empty

SPI transmitter CPU interrupt request

(DMAS= 0, SPTIE= 1, SPE= 1)

SPRF

Receiver full

SPI receiver CPU interrupt request

(DMAS= 0, SPRIE=1)

OVRF

Overflow

SPI receiver/error interrupt request (ERRIE = 1)

MODF

Mode fault

SPI receiver/error interrupt request (ERRIE = 1)

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