M68ICS08GR datasheet(318/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

318

Serial Peripheral Interface (SPI)

MOTOROLA

20.12 SPI During Break Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state. See System Integration Module (SIM).

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing procedure. If software does

the first step on such a bit before the break, the bit cannot change during

the break state as long as BCFE is at logic 0. After the break, doing the

second step clears the status bit.

Since the SPTE bit cannot be cleared during a break with the BCFE bit

cleared, a write to the transmit data register in break mode does not

initiate a transmission nor is this data transferred into the shift register.

Therefore, a write to the SPDR in break mode with the BCFE bit cleared

has no effect.

20.13 I/O Signals

The SPI module has five I/O pins and shares four of them with a parallel

I/O port. They are:

•

MISO — Data received

•

MOSI — Data transmitted

•

SPSCK — Serial clock

•

SS — Slave select

•

CGND — Clock ground (internally connected to VSS)

The SPI has limited inter-integrated circuit (I2C) capability (requiring

software support) as a master in a single-master environment. To

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