M68ICS08GR datasheet(319/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

I/O Signals

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

319

communicate with I2C peripherals, MOSI becomes an open-drain output

when the SPWOM bit in the SPI control register is set. In I2C

communication, the MOSI and MISO pins are connected to a

bidirectional pin from the I2C peripheral and through a pullup resistor to

VDD.

20.13.1 MISO (Master In/Slave Out)

MISO is one of the two SPI module pins that transmits serial data. In full

duplex operation, the MISO pin of the master SPI module is connected

to the MISO pin of the slave SPI module. The master SPI simultaneously

receives data on its MISO pin and transmits data from its MOSI pin.

Slave output data on the MISO pin is enabled only when the SPI is

configured as a slave. The SPI is configured as a slave when its

SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-

slave system, a logic 1 on the SS pin puts the MISO pin in a high-

impedance state.

When enabled, the SPI controls data direction of the MISO pin

regardless of the state of the data direction register of the shared I/O

port.

20.13.2 MOSI (Master Out/Slave In)

MOSI is one of the two SPI module pins that transmits serial data. In full-

duplex operation, the MOSI pin of the master SPI module is connected

to the MOSI pin of the slave SPI module. The master SPI simultaneously

transmits data from its MOSI pin and receives data on its MISO pin.

When enabled, the SPI controls data direction of the MOSI pin

regardless of the state of the data direction register of the shared I/O

port.

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M68ICS08GR Datasheet(PDF) 319 Page - Freescale Semiconductor, Inc