M68ICS08GR datasheet(321/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

I/O Signals

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

321

When an SPI is configured as a master, the SS input can be used in

conjunction with the MODF flag to prevent multiple masters from driving

MOSI and SPSCK. See Mode Fault Error. For the state of the SS pin to

set the MODF flag, the MODFEN bit in the SPSCK register must be set.

If the MODFEN bit is low for an SPI master, the SS pin can be used as

a general-purpose I/O under the control of the data direction register of

the shared I/O port. With MODFEN high, it is an input-only pin to the SPI

regardless of the state of the data direction register of the shared I/O

port.

The CPU can always read the state of the SS pin by configuring the

appropriate pin as an input and reading the port data register. See Table

20-3.

20.13.5 CGND (Clock Ground)

CGND is the ground return for the serial clock pin, SPSCK, and the

ground for the port output buffers. It is internally connected to VSS as

shown in Table 20-1.

Table 20-3. SPI Configuration

SPE

SPMSTR

MODFEN

SPI Configuration

State of SS Logic

X(1)

Not enabled

General-purpose I/O;

SS ignored by SPI

Slave

Input-only to SPI

Master without MODF

General-purpose I/O;

SS ignored by SPI

Master with MODF

Input-only to SPI

Note 1. X = Don’t care

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