M68ICS08GR datasheet(323/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

323

SPRIE — SPI Receiver Interrupt Enable Bit

This read/write bit enables CPU interrupt requests generated by the

SPRF bit. The SPRF bit is set when a byte transfers from the shift

1 = SPRF CPU interrupt requests enabled

0 = SPRF CPU interrupt requests disabled

DMAS —DMA Select Bit

This read only bit has no effect on this version of the SPI. This bit

always reads as a 0.

0 = SPRF DMA and SPTE DMA service requests disabled

(SPRF CPU and SPTE CPU interrupt requests enabled)

SPMSTR — SPI Master Bit

This read/write bit selects master mode operation or slave mode

operation. Reset sets the SPMSTR bit.

1 = Master mode

0 = Slave mode

CPOL — Clock Polarity Bit

This read/write bit determines the logic state of the SPSCK pin

between transmissions. (See Figure 20-4 and Figure 20-6.) To

transmit data between SPI modules, the SPI modules must have

identical CPOL values. Reset clears the CPOL bit.

CPHA — Clock Phase Bit

This read/write bit controls the timing relationship between the serial

clock and SPI data. (See Figure 20-4 and Figure 20-6.) To transmit

data between SPI modules, the SPI modules must have identical

CPHA values. When CPHA = 0, the SS pin of the slave SPI module

must be set to logic 1 between bytes. See Figure 20-12. Reset sets

the CPHA bit.

SPWOM — SPI Wired-OR Mode Bit

This read/write bit disables the pullup devices on pins SPSCK, MOSI,

and MISO so that those pins become open-drain outputs.

1 = Wired-OR SPSCK, MOSI, and MISO pins

0 = Normal push-pull SPSCK, MOSI, and MISO pins

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