SPC5668EF1AVMGR datasheet(44/66 Pages) FREESCALE

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MPC5668x Microcontroller Data Sheet, Rev. 6

Electrical Characteristics

Freescale Semiconductor

4.14.3

JTAG (IEEE 1149.1) Interface

Figure 9. JTAG Test Clock Input Timing

Table 26. JTAG Interface Timing1

1 These specifications apply to JTAG boundary scan only. JTAG timing specified at V

DDE =3.0–5.5 V, TA =TL to TH, and

CL = 30 pF with SRC = 0b11.

Spec

Characteristic

Symbol

Min

Max

Unit

TCK Cycle Time

tJCYC

100

—

TCK Clock Pulse Width (Measured at VDDE/2)

tJDC

TCK Rise and Fall Times (40% – 70%)

tTCKRISE

—3

TMS, TDI Data Setup Time

tTMSS, tTDIS

5—

TMS, TDI Data Hold Time

tTMSH, tTDIH

—

TCK Low to TDO Data Valid

tTDOV

—25

TCK Low to TDO Data Invalid

tTDOI

0—

TCK Low to TDO High Impedance

tTDOHZ

—20

JCOMP Assertion Time

tJCMPPW

100

—

JCOMP Setup Time to TCK Low

tJCMPS

—

TCK Falling Edge to Output Valid

tBSDV

—50

TCK Falling Edge to Output Valid out of High Impedance

tBSDVZ

—50

TCK Falling Edge to Output High Impedance

tBSDHZ

—50

Boundary Scan Input Valid to TCK Rising Edge

tBSDST

—

TCK Rising Edge to Boundary Scan Input Invalid

tBSDHT

—

TCK

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