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DSPIC33FJ12MC201TESS Datasheet(PDF) 207 Page - Microchip Technology

Part # DSPIC33FJ12MC201TESS
Description  High-Performance, 16-bit Digital Signal Controllers
PDF  304 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33FJ12MC201TESS Datasheet(HTML) 207 Page - Microchip Technology

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© 2007-2011 Microchip Technology Inc.
DS70265E-page 207
dsPIC33FJ12MC201/202
FWDTEN
FWDT
Immediate Watchdog Timer Enable bit
1
= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0
= Watchdog Timer enabled/disabled by user software (LPRC can be dis-
abled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
Immediate Watchdog Timer Window Enable bit
1
= Watchdog Timer in Non-Window mode
0
= Watchdog Timer in Window mode
WDTPRE
FWDT
Immediate Watchdog Timer Prescaler bit
1
= 1:128
0
= 1:32
WDTPOST<3:0>
FWDT
Immediate Watchdog Timer Postscaler bits
1111
= 1:32,768
1110
= 1:16,384
•
•
•
0001
= 1:2
0000
= 1:1
PWMPIN
FPOR
Immediate Motor Control PWM Module Pin Mode bit
1
= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0
= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
HPOL
FPOR
Immediate Motor Control PWM High Side Polarity bit
1
= PWM module high side output pins have active-high output polarity
0
= PWM module high side output pins have active-low output polarity
LPOL
FPOR
Immediate Motor Control PWM Low Side Polarity bit
1
= PWM module low side output pins have active-high output polarity
0
= PWM module low side output pins have active-low output polarity
FPWRT<2:0>
FPOR
Immediate Power-on Reset Timer Value Select bits
111
= PWRT = 128 ms
110
= PWRT = 64 ms
101
= PWRT = 32 ms
100
= PWRT = 16 ms
011
= PWRT = 8 ms
010
= PWRT = 4 ms
001
= PWRT = 2 ms
000
= PWRT = Disabled
ALTI2C
FPOR
Immediate Alternate I2C pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
JTAGEN
FICD
Immediate JTAG Enable bit
1
= JTAG enabled
0
= JTAG disabled
ICS<1:0>
FICD
Immediate ICD Communication Channel Select bits
11
= Communicate on PGEC1 and PGED1
10
= Communicate on PGEC2 and PGED2
01
= Communicate on PGEC3 and PGED3
00
= Reserved, do not use
TABLE 21-2:
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
RTSP
Effect
Description



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