PIC16F1459-ESSQTP datasheet(208/418 Pages) MICROCHIP

208 / 418 page

PIC16(L)F1454/5/9

DS41639A-page 208

Preliminary

 2012 Microchip Technology Inc.

22.2.2

SPI MODE OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN of the

SSPCON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSPCONx registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

•SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the eight bits of

data have been received, that byte is moved to the

SSPBUF register. Then, the Buffer Full Detect bit, BF

of the SSPSTAT register, and the interrupt flag bit,

SSPIF, are set. This double-buffering of the received

data (SSPBUF) allows the next byte to start reception

before reading the data that was just received. Any

write

the

SSPBUF

during

transmission/reception of data will be ignored and the

write collision detect bit WCOL of the SSPCON1

WCOL bit to allow the following write(s) to the SSPBUF

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF of the SSPSTAT register, indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur.

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSPSTAT register indicates the

various Status conditions.

FIGURE 22-5:

SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(BUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

Slave Select

General I/O

(optional)

= 1010

PIC16F1459-ESSQTP Datasheet(PDF) 208 Page - Microchip Technology

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