PIC16F1459-ESSQTP datasheet(237/418 Pages) MICROCHIP

237 / 418 page

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 237

PIC16(L)F1454/5/9

22.6.4

C MASTER MODE START

CONDITION TIMING

To initiate a Start condition (Figure 22-26), the user

sets the Start Enable bit, SEN bit of the SSPCON2

the Baud Rate Generator is reloaded with the contents

of SSPADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT1

erator is reloaded with the contents of SSPADD<7:0>

and resumes its count. When the Baud Rate Genera-

tor times out (TBRG), the SEN bit of the SSPCON2 reg-

ister will be automatically cleared by hardware; the

Baud Rate Generator is suspended, leaving the SDA

line held low and the Start condition is complete.

FIGURE 22-26:

FIRST START BIT TIMING

Note 1:

If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is

aborted and the I2C module is reset into

its Idle state.

The Philips I2C™ Specification states that

a bus collision cannot occur on a Start.

SDA

SCL

TBRG

1st bit

2nd bit

TBRG

SDA = 1,

At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPSTAT<3>)

and sets SSPIF bit

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