PIC16F1459-ESSQTP datasheet(116/418 Pages) MICROCHIP

116 / 418 page

PIC16(L)F1454/5/9

DS41639A-page 116

Preliminary

 2012 Microchip Technology Inc.

11.2.3

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be

erased by rows. To erase a row:

Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

Clear the CFGS bit of the PMCON1 register.

Set the FREE and WREN bits of the PMCON1

Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

Set control bit WR of the PMCON1 register to

begin the erase operation.

See Example 11-2.

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOP instructions immediately fol-

lowing the WR bit set instruction. The processor will

halt internal operations for the typical 2 ms erase time.

This is not Sleep mode as the clocks and peripherals

will continue to run. After the erase cycle, the processor

will resume operation with the third instruction after the

PMCON1 write instruction.

FIGURE 11-4:

FLASH PROGRAM

MEMORY ERASE

FLOWCHART

Disable Interrupts

(GIE = 0)

Start

Erase Operation

Select

Program or Configuration Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(FIGURE x-x)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

CPU stalls while

Erase operation completes

(2ms typical)

Figure 11-3

PIC16F1459-ESSQTP Datasheet(PDF) 116 Page - Microchip Technology

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