DSPIC33FJ06GS202 datasheet(16/20 Pages) MICROCHIP

16 / 20 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS80439M-page 16

 2009-2013 Microchip Technology Inc.

44. Module: PWM

If the PWM is configured for Complimentary mode

and the SWAP bit is enabled, the PWM outputs

might operate as Redundant mode when the

PHASE value is greater than the programmed

dead-time (DTRx) value.

Work around

Using true independent output mode with the

independent Time Base mode bit (ITB) set to ‘0’,

the PWM module can be configured to replicate

the original complementary signal by properly

setting up the phase (PHASEx, SPASEx) and the

independent duty cycle (PDCx, SDCx).

Affected Silicon Revisions

45. Module: PWM

The PWM current-limit operation allows the PWM

module to set/reset the output signals when a

specific current limit is detected with a minimum

latency delay. When operating the PWM module in

Complementary mode (PMOD = 0), positive dead

time, and with Current-Limit Interrupt Enable

(CLIEN = 1), a less than 8-ns pulse glitch on the

complementary output may be present right after

the current limit is detected. This glitch, if present,

will occur prior to the implementation of the dead

time.

Work around

In order to avoid the <8 ns glitch to be propagated

into the MOSFET gate driver, a low-pass filter

(e.g., resistor-capacitor network) should be

implemented between the dsPIC® DSC PWM

output pin and the gate driver IC input pin.

Affected Silicon Revisions

DSPIC33FJ06GS202 Datasheet(PDF) 16 Page - Microchip Technology