MC68HC908GR4MP datasheet(325/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Peripheral Interface (SPI)

325

SPRF — SPI Receiver Full Bit

This clearable, read-only flag is set each time a byte transfers from

the shift register to the receive data register. SPRF generates a CPU

interrupt request if the SPRIE bit in the SPI control register is set also.

During an SPRF CPU interrupt, the CPU clears SPRF by reading the

SPI status and control register with SPRF set and then reading the

SPI data register.

Reset clears the SPRF bit.

1 = Receive data register full

0 = Receive data register not full

ERRIE — Error Interrupt Enable Bit

This read/write bit enables the MODF and OVRF bits to generate

CPU interrupt requests. Reset clears the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests

0 = MODF and OVRF cannot generate CPU interrupt requests

OVRF — Overflow Bit

This clearable, read-only flag is set if software does not read the byte

in the receive data register before the next full byte enters the shift

OVRF bit by reading the SPI status and control register with OVRF set

and then reading the receive data register. Reset clears the OVRF bit.

1 = Overflow

0 = No overflow

Address: $0011

Bit 7

654321

Bit 0

Read:

SPRF

ERRIE

OVRF

MODF

SPTE

MODFEN

SPR1

SPR0

Write:

Reset:

00001000

= Unimplemented

Figure 20-14. SPI Status and Control Register (SPSCR)

Freescale Semiconductor, Inc.

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MC68HC908GR4MP Datasheet(PDF) 325 Page - Freescale Semiconductor, Inc

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