DSPIC30F2011AT-30ESLASHPF datasheet(151/228 Pages) MICROCHIP

151 / 228 page

DS70117F-page 149

dsPIC30F6011/6012/6013/6014

20.2.4

PHASE LOCKED LOOP (PLL)

The PLL multiplies the clock which is generated by the

primary oscillator. The PLL is selectable to have either

gains of x4, x8, and x16. Input and output frequency

ranges are summarized in Table 20-3.

TABLE 20-3:

PLL FREQUENCY RANGE

The PLL features a lock output which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read only LOCK bit in the OSCCON register.

20.2.5

FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (7.37 MHz ±2% nominal)

internal RC oscillator. This oscillator is intended to pro-

vide reasonable device operating speeds without the

use of an external crystal, ceramic resonator, or RC

network.

The dsPIC30F operates from the FRC oscillator when-

ever the current oscillator selection control bits in the

OSCCON register (COSC<13:12>) are set to ‘01’.

The four bit field specified by TUN<3:0> (OSCCON

<15:14> and OSCCON<11:10>) allows the user to tune

the internal fast RC oscillator (nominal 7.37MHz). The

user can tune the FRC oscillator within a range of -12%

(or -960 kHz) to +10.5% (or +840 kHz) in steps of

1.50% around the factory-calibrated setting, see

Table 20-4.

TABLE 20-4:

FRC TUNING

20.2.6

LOW POWER RC OSCILLATOR

(LPRC)

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT, and clock

monitor circuits. It may also be used to provide a low

frequency clock source option for applications where

power consumption is critical and timing accuracy is

not required

The LPRC oscillator is always enabled at a Power-on

Reset because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will

remain on if one of the following is TRUE:

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

• The LPRC oscillator is selected as the system

clock via the COSC<1:0> control bits in the

OSCCON register

If one of the above conditions is not true, the LPRC will

shut off after the PWRT expires.

20.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM Configuration bits (clock

switch and monitor selection bits) in the FOSC Device

Configuration register. If the FSCM function is enabled,

the LPRC internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control by

the SWDTEN bit.

In the event of an oscillator failure, the FSCM will gen-

erate a clock failure trap event and will switch the sys-

tem clock over to the FRC oscillator. The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) status bit (OSCCON<3>) is

also set whenever a clock failure is recognized.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

FIN

PLL

Multiplier

FOUT

4 MHz-10 MHz

16 MHz-40 MHz

4 MHz-10 MHz

32 MHz-80 MHz

4 MHz-7.5 MHz

x16

64 MHz-120 MHz

TUN<3:0>Bits

FRC Frequency

0111

+ 10.5%

0110

+ 9.0%

0101

+ 7.5%

0100

+ 6.0%

0011

+ 4.5%

0010

+ 3.0%

0001

+ 1.5%

0000

Center Frequency (oscillator is

running at calibrated frequency)

1111

- 1.5%

1110

- 3.0%

1101

- 4.5%

1100

- 6.0%

1011

- 7.5%

1010

- 9.0%

1001

- 10.5%

1000

- 12.0%

Note 1: OSC2 pin function is determined by the

Primary

Oscillator

mode

selection

(FPR<3:0>).

2: OSC1 pin cannot be used as an I/O pin

even if the secondary oscillator or an

internal clock source is selected at all

times.

DSPIC30F2011AT-30E/PF Datasheet(PDF) 151 Page - Microchip Technology

DSPIC30F2011AT-30E/PF Datasheet(HTML) 151 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL