AD5381BSTZ-5 datasheet(21/40 Pages) AD

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Data Sheet

AD5381

Rev. D | Page 21 of 40

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5381 is a complete, single-supply, 40-channel voltage

output DACthat offers12-bit resolution. The part is available

in a 100-lead LQFP package and features both a parallel and

a serial interface. This product includes an internal, software

selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used

to drive the bufferedreference inputs; alternatively, an external

referencecan be used to drive theseinputs. Internal/external

referenceselection is via the CR8 bit in the control register;

CR10 selects the referencemagnitude if the internal reference

is selected. All channels have an on-chip output amplifier with

rail-to-rail outputcapable of driving 5 kΩ in parallel with a

200 pF load.

VOUT

12-BIT

DAC

REG

m REG

c REG

×1 INPUT

REG

×2

INPUT DATA

VREF

AVDD

Figure 27. Single-Channel Architecture

The architecture of a single DACchannel consists ofa 12-bit

resistor-string DACfollowed by an outputbuffer amplifier

operating at a gain of 2. This resistor-string architecture

guaranteesDAC monotonicity. The 12-bit binary digital code

loaded to the DAC registerdetermines at whatnode on the

string the voltage is tapped off beforebeing fed to the output

amplifier. Each channel on these devices contains independent

offset and gain control registers that allow theuser to digitally

trim offset and gain. These registers give the userthe ability to

calibrate out errors in the completesignal chain, including the

DAC, using the internal m and cregisters, which hold the

correction factors. All channels are double buffered, allow-

ing synchronous updating of all channels using the LDACpin.

Figure 27 shows a blockdiagram of a single channel on the

AD5381. The digital input transfer function for each DAC

can be represented as

x2 = [(m + 2)/ 2n × x1] + (c – 2n – 1)

where:

x2 = the data-wordloadedto the resistorstring DAC.

x1 = the 12-bit data-wordwritten to the DACinput register.

m = the gain coefficient (default is 0xFFE). The gain coefficient

is written to the 11 most significant bits (DB11 to DB1), the LSB

(DB0)of the data-wordis a 0.

n = DAC resolution (n = 12 for AD5381).

c = the12-bit offset coefficient (default is 0x800).

The complete transfer function for thesedevices can be

represented as

VOUT = 2 × V

REF × x2/2

where:

x2 is the data-word loaded to the resistor string DAC. V

REF

is externally applied to the DACREFOUT/REFINpin. For

specified performance, an external reference voltageof 2.5 V is

recommendedfor the AD5381-5, and 1.25 V for the AD5381-3.

DATA DECODING

The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-

ing on the value of REG1 and REG0 (see Table 10), this data is

loaded into the addressedDACinput registers, offset (c)

registers, or gain (m)registers. The format data, offset (c), and

gain (m) register contents areshown in Table 11 to Table 13.

Table 10. Register Selection

REG1

REG0

Input Data Register (x1)

Offset Register (c)

Gain Register (m)

Special Function Registers (SFRs)

Table 11. DAC Data Format(REG1 = 1, REG0 = 1)

DB11 to DB0

DAC Output (V)

1111

2 V

REF × (4095/4096)

1111

1110

2 V

REF × (4094/4096)

1000

0000

0001

2 V

REF × (2049/4096)

1000

0000

2 V

REF × (2048/4096)

0111

1111

2 V

REF × (2047/4096)

0000

0001

2 V

REF × (1/4096)

0000

Table 12. OffsetData Format (REG1 = 1, REG0 = 0)

DB11 to DB0

Offset (LSB)

1111

+2048

1111

1110

+2047

1000

0000

0001

1000

0000

0111

1111

–1

0000

0001

–2047

0000

–2048

Table 13. GainData Format(REG1 = 0, REG0 = 1)

DB11 to DB0

Gain Factor

1111

1110

1011

1111

1110

0.75

0111

1111

1110

0.5

0011

1111

1110

0.25

0000

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