S25FS256S datasheet(97/154 Pages) SPANSION

97 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

Notes:

1. The Status Register originally shows 00h when the device is first shipped from Spansion to the customer.

2. Hardware protection is disabled when Quad Mode is enabled (CR1V[1] = 1). WP# becomes IO2; therefore, it cannot be utilized.

10.3.5

Write Enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1

(SR1V[1]) to a 0. The Write Enable Latch (WEL) bit must be set to a 1 by issuing the Write Enable (WREN)

command to enable write, program and erase commands.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on

SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched

in on SI, the write enable operation will not be executed.

Figure 10.13 Write Enable (WREN) Command Sequence

This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock

cycles per byte.

Figure 10.14 Write Enable (WREN) Command Sequence QPI Mode

Table 10.2 Block Protection Modes

WP#

SRWD

Bit

Mode

Write Protection of Registers

Memory Content

Protected Area

Unprotected Area

Software

Protected

Status and Configuration Registers are Writable (if

WREN command has set the WEL bit). The values

in the SRWD, BP2, BP1, and BP0 bits and those in

the Configuration Register can be changed.

Protected against

Page Program,

Sector Erase, and

Bulk Erase.

Ready to accept

Page Program, and

Sector Erase

commands.

Hardware

Protected

Status and Configuration Registers are Hardware

Write Protected. The values in the SRWD, BP2,

BP1, and BP0 bits and those in the Configuration

Protected against

Page Program,

Sector Erase, and

Bulk Erase.

Ready to accept

Page Program or

Erase commands.

CS#

SCK

Phase

Instruction

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

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