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PIC18F4550ESPQTP Datasheet(PDF) 55 Page - Microchip Technology |
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PIC18F4550ESPQTP Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 438 page  © 2009 Microchip Technology Inc. DS39632E-page 53 PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1) TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1) STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2(3) TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu(2) INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u(2) INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu(2) INDF0 2455 2550 4455 4550 N/A N/A N/A POSTINC0 2455 2550 4455 4550 N/A N/A N/A POSTDEC0 2455 2550 4455 4550 N/A N/A N/A PREINC0 2455 2550 4455 4550 N/A N/A N/A PLUSW0 2455 2550 4455 4550 N/A N/A N/A FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2455 2550 4455 4550 N/A N/A N/A POSTINC1 2455 2550 4455 4550 N/A N/A N/A POSTDEC1 2455 2550 4455 4550 N/A N/A N/A PREINC1 2455 2550 4455 4550 N/A N/A N/A PLUSW1 2455 2550 4455 4550 N/A N/A N/A FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 4: See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. |
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