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PIC18F4550ESOSQTP Datasheet(PDF) 431 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 431 Page - Microchip Technology |
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431 / 438 page  © 2009 Microchip Technology Inc. DS39632E-page 429 PIC18F2455/2550/4455/4550 Program Memory and the Extended Instruction Set ............................... 77 Code Protection ....................................................... 309 Instructions ................................................................. 64 Two-Word .......................................................... 64 Interrupt Vector .......................................................... 59 Look-up Tables .......................................................... 62 Map and Stack (diagram) ........................................... 59 Reset Vector .............................................................. 59 Program Verification and Code Protection ....................... 308 Associated Registers ............................................... 308 Programming, Device Instructions ................................... 313 Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 342 PUSH and POP Instructions .............................................. 61 PUSHL ............................................................................. 358 PWM (CCP Module) Associated Registers ............................................... 150 Auto-Shutdown (CCP1 Only) ................................... 149 Duty Cycle ................................................................ 148 Example Frequencies/Resolutions .......................... 149 Period ....................................................................... 148 Setup for PWM Operation ........................................ 149 TMR2 to PR2 Match ................................................ 148 PWM (ECCP Module) ...................................................... 153 CCPR1H:CCPR1L Registers ................................... 153 Direction Change in Full-Bridge Output Mode ......... 158 Duty Cycle ................................................................ 154 Effects of a Reset ..................................................... 163 Enhanced PWM Auto-Shutdown ............................. 160 Enhanced PWM Mode ............................................. 153 Example Frequencies/Resolutions .......................... 154 Full-Bridge Application Example .............................. 158 Full-Bridge Mode ...................................................... 157 Half-Bridge Mode ..................................................... 156 Half-Bridge Output Mode Applications Example ...................................... 156 Operation in Power-Managed Modes ...................... 163 Operation with Fail-Safe Clock Monitor ................... 163 Output Configurations .............................................. 154 Output Relationships (Active-High) .......................... 155 Output Relationships (Active-Low) ........................... 155 Period ....................................................................... 153 Programmable Dead-Band Delay ............................ 160 Setup for PWM Operation ........................................ 163 Start-up Considerations ........................................... 162 TMR2 to PR2 Match ................................................ 153 Q Q Clock .................................................................... 149, 154 R RAM. See Data Memory. RC_IDLE Mode .................................................................. 42 RC_RUN Mode .................................................................. 38 RCALL ............................................................................. 343 RCON Register Bit Status During Initialization .................................... 52 Reader Response ............................................................ 434 Register File ....................................................................... 67 Register File Summary ................................................ 69–72 Registers ADCON0 (A/D Control 0) ......................................... 265 ADCON1 (A/D Control 1) ......................................... 266 ADCON2 (A/D Control 2) ......................................... 267 BAUDCON (Baud Rate Control) .............................. 246 BDnSTAT (Buffer Descriptor n Status, CPU Mode) ...................................................... 176 BDnSTAT (Buffer Descriptor n Status, SIE Mode) ....................................................... 177 CCP1CON (ECCP Control) ..................................... 151 CCPxCON (Standard CCPx Control) ...................... 143 CMCON (Comparator Control) ................................ 275 CONFIG1H (Configuration 1 High) .......................... 294 CONFIG1L (Configuration 1 Low) ........................... 293 CONFIG2H (Configuration 2 High) .......................... 296 CONFIG2L (Configuration 2 Low) ........................... 295 CONFIG3H (Configuration 3 High) .......................... 297 CONFIG4L (Configuration 4 Low) ........................... 298 CONFIG5H (Configuration 5 High) .......................... 299 CONFIG5L (Configuration 5 Low) ........................... 299 CONFIG6H (Configuration 6 High) .......................... 300 CONFIG6L (Configuration 6 Low) ........................... 300 CONFIG7H (Configuration 7 High) .......................... 301 CONFIG7L (Configuration 7 Low) ........................... 301 CVRCON (Comparator Voltage Reference Control) .......................................... 281 DEVID1 (Device ID 1) .............................................. 302 DEVID2 (Device ID 2) .............................................. 302 ECCP1AS (Enhanced Capture/Compare/PWM Auto-Shutdown Control) .................................. 161 ECCP1DEL (PWM Dead-Band Delay) .................... 160 EECON1 (Data EEPROM Control 1) ................... 83, 92 HLVDCON (High/Low-Voltage Detect Control) ....... 285 INTCON (Interrupt Control) ..................................... 101 INTCON2 (Interrupt Control 2) ................................ 102 INTCON3 (Interrupt Control 3) ................................ 103 IPR1 (Peripheral Interrupt Priority 1) ....................... 108 IPR2 (Peripheral Interrupt Priority 2) ....................... 109 OSCCON (Oscillator Control) .................................... 33 OSCTUNE (Oscillator Tuning) ................................... 28 PIE1 (Peripheral Interrupt Enable 1) ....................... 106 PIE2 (Peripheral Interrupt Enable 2) ....................... 107 PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 104 PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 105 PORTE .................................................................... 125 RCON (Reset Control) ....................................... 46, 110 RCSTA (Receive Status and Control) ..................... 245 SPPCFG (SPP Configuration) ................................. 192 SPPCON (SPP Control) .......................................... 191 SPPEPS (SPP Endpoint Address and Status) ........ 195 SSPCON1 (MSSP Control 1, I2C Mode) ................. 209 SSPCON1 (MSSP Control 1, SPI Mode) ................ 199 SSPCON2 (MSSP Control 2, I2C Master Mode) ............................................ 210 SSPCON2 (MSSP Control 2, I2C Slave Mode) ....... 211 SSPSTAT (MSSP Status, I2C Mode) ...................... 208 SSPSTAT (MSSP Status, SPI Mode) ...................... 198 STATUS .................................................................... 73 STKPTR (Stack Pointer) ............................................ 61 T0CON (Timer0 Control) ......................................... 127 T1CON (Timer1 Control) ......................................... 131 T2CON (Timer2 Control) ......................................... 137 T3CON (Timer3 Control) ......................................... 139 |
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