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PIC18F4550ESOSQTP Datasheet(PDF) 433 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 433 Page - Microchip Technology |
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433 / 438 page ![]() © 2009 Microchip Technology Inc. DS39632E-page 431 PIC18F2455/2550/4455/4550 TMR1H Register ...................................................... 131 TMR1L Register ....................................................... 131 Use as a Real-Time Clock ....................................... 134 Timer2 .............................................................................. 137 Associated Registers ............................................... 138 Interrupt .................................................................... 138 Operation ................................................................. 137 Output ...................................................................... 138 PR2 Register .................................................... 148, 153 TMR2 to PR2 Match Interrupt .......................... 148, 153 Timer3 .............................................................................. 139 16-Bit Read/Write Mode ........................................... 141 Associated Registers ............................................... 141 Operation ................................................................. 140 Oscillator .......................................................... 139, 141 Overflow Interrupt ............................................ 139, 141 Special Event Trigger (CCP) .................................... 141 TMR3H Register ...................................................... 139 TMR3L Register ....................................................... 139 Timing Diagrams A/D Conversion ........................................................ 404 Acknowledge Sequence .......................................... 235 Asynchronous Reception (TXCKP = 0, TX Not Inverted) .............................................. 257 Asynchronous Transmission (TXCKP = 0, TX Not Inverted) .............................................. 254 Asynchronous Transmission, Back to Back (TXCKP = 0, TX Not Inverted) ......................... 254 Automatic Baud Rate Calculation ............................ 252 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 258 Auto-Wake-up Bit (WUE) During Sleep ................... 258 Baud Rate Generator with Clock Arbitration ............ 229 BRG Overflow Sequence ......................................... 252 BRG Reset Due to SDA Arbitration During Start Condition ................................................. 238 Brown-out Reset (BOR) ........................................... 390 Bus Collision During a Repeated Start Condition (Case 1) ........................................... 239 Bus Collision During a Repeated Start Condition (Case 2) ........................................... 239 Bus Collision During a Start Condition (SCL = 0) ......................................................... 238 Bus Collision During a Start Condition (SDA Only) ....................................................... 237 Bus Collision During a Stop Condition (Case 1) ........................................................... 240 Bus Collision During a Stop Condition (Case 2) ........................................................... 240 Bus Collision for Transmit and Acknowledge ........... 236 Capture/Compare/PWM (All CCP Modules) ............ 392 CLKO and I/O .......................................................... 389 Clock Synchronization ............................................. 222 Clock/Instruction Cycle .............................................. 63 EUSART Synchronous Receive (Master/Slave) ................................................. 401 EUSART Synchronous Transmission (Master/Slave) ................................................. 401 Example SPI Master Mode (CKE = 0) ..................... 393 Example SPI Master Mode (CKE = 1) ..................... 394 Example SPI Slave Mode (CKE = 0) ....................... 395 Example SPI Slave Mode (CKE = 1) ....................... 396 External Clock (All Modes Except PLL) ................... 387 Fail-Safe Clock Monitor ............................................ 307 First Start Bit Timing ................................................ 230 Full-Bridge PWM Output .......................................... 157 Half-Bridge PWM Output ......................................... 156 High/Low-Voltage Detect Characteristics ................ 384 High-Voltage Detect (VDIRMAG = 1) ...................... 288 I2C Bus Data ............................................................ 397 I2C Bus Start/Stop Bits ............................................ 397 I2C Master Mode (7 or 10-Bit Transmission) ........... 233 I2C Master Mode (7-Bit Reception) ......................... 234 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK 01001) ................................ 219 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 218 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 224 I2C Slave Mode (10-Bit Transmission) .................... 220 I2C Slave Mode (7-bit Reception, SEN = 0, ADMSK = 01011) ............................. 216 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 215 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 223 I2C Slave Mode (7-Bit Transmission) ...................... 217 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 225 Low-Voltage Detect (VDIRMAG = 0) ....................... 287 Master SSP I2C Bus Data ....................................... 399 Master SSP I2C Bus Start/Stop Bits ........................ 399 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 162 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 162 PWM Direction Change ........................................... 159 PWM Direction Change at Near 100% Duty Cycle ............................................. 159 PWM Output ............................................................ 148 Repeated Start Condition ........................................ 231 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 390 Send Break Character Sequence ............................ 259 Slave Synchronization ............................................. 204 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 51 SPI Mode (Master Mode) ........................................ 203 SPI Mode (Slave Mode with CKE = 0) ..................... 205 SPI Mode (Slave Mode with CKE = 1) ..................... 205 SPP Write Address and Data for USB (4 Wait States) ................................................. 193 SPP Write Address and Read Data for USB (4 Wait States) ........................................ 193 SPP Write Address, Write and Read Data (No Wait States) ...................................... 193 Stop Condition Receive or Transmit Mode .............. 235 Streaming Parallel Port (PIC18F4455/4550) ........... 403 Synchronous Reception (Master Mode, SREN) ...... 262 Synchronous Transmission ..................................... 260 Synchronous Transmission (Through TXEN) .......... 261 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) .......................................... 51 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ...................... 50 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ...................... 50 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 50 Timer0 and Timer1 External Clock .......................... 391 Transition for Entry to Idle Mode ............................... 41 Transition for Entry to SEC_RUN Mode .................... 37 Transition for Entry to Sleep Mode ............................ 40 |
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