PIC18F4550ESOSQTP datasheet(434/438 Pages) MICROCHIP

434 / 438 page

PIC18F2455/2550/4455/4550

DS39632E-page 432

Transition for Two-Speed Start-up

(INTOSC to HSPLL) ......................................... 305

Transition for Wake From Idle to Run Mode .............. 41

Transition for Wake from Sleep (HSPLL) ................... 40

Transition From RC_RUN Mode to

PRI_RUN Mode ................................................. 39

Transition from SEC_RUN Mode to

PRI_RUN Mode (HSPLL) .................................. 37

Transition to RC_RUN Mode ..................................... 39

USB Signal ............................................................... 402

Timing Diagrams and Specifications ................................ 387

Capture/Compare/PWM Requirements

(All CCP Modules) ........................................... 392

CLKO and I/O Requirements ................................... 389

EUSART Synchronous Receive

Requirements ................................................... 401

EUSART Synchronous Transmission

Requirements ................................................... 401

Example SPI Mode Requirements

(Master Mode, CKE = 0) .................................. 393

Example SPI Mode Requirements

(Master Mode, CKE = 1) .................................. 394

Example SPI Mode Requirements

(Slave Mode, CKE = 0) .................................... 395

Example SPI Mode Requirements

(Slave Mode, CKE = 1) .................................... 396

External Clock Requirements .................................. 387

I2C Bus Data Requirements (Slave Mode) .............. 398

I2C Bus Start/Stop Bits Requirements ..................... 397

Master SSP I2C Bus Data Requirements ................ 400

Master SSP I2C Bus Start/Stop Bits

Requirements ................................................... 399

PLL Clock ................................................................. 388

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and

Brown-out Reset Requirements ....................... 390

Streaming Parallel Port Requirements

(PIC18F4455/4550) ......................................... 403

Timer0 and Timer1 External Clock

Requirements ................................................... 391

USB Full-Speed Requirements ................................ 402

USB Low-Speed Requirements ............................... 402

Top-of-Stack Access .......................................................... 60

TQFP Packages and Special Features ............................ 311

TSTFSZ ............................................................................ 353

Two-Speed Start-up ................................................. 291, 305

Two-Word Instructions

Example Cases .......................................................... 64

TXSTA Register

BRGH Bit ................................................................. 247

Universal Serial Bus ........................................................... 65

Address Register (UADDR) ..................................... 173

and Streaming Parallel Port ..................................... 187

Associated Registers ............................................... 187

Buffer Descriptor Table ............................................ 174

Buffer Descriptors .................................................... 174

Address Validation ........................................... 177

Assignment in Different Buffering Modes ........ 179

BDnSTAT Register (CPU Mode) ..................... 175

BDnSTAT Register (SIE Mode) ....................... 177

Byte Count ....................................................... 177

Example ........................................................... 174

Memory Map .................................................... 178

Ownership ....................................................... 174

Ping-Pong Buffering ........................................ 178

Status and Configuration ................................. 174

Class Specifications and Drivers ............................. 190

Descriptors ............................................................... 190

Endpoint Control ...................................................... 172

Enumeration ............................................................ 190

External Pull-up Resistors ....................................... 169

External Transceiver ................................................ 167

Eye Pattern Test Enable .......................................... 169

Firmware and Drivers .............................................. 187

Frame Number Registers ........................................ 173

Frames .................................................................... 189

Internal Pull-up Resistors ......................................... 169

Internal Transceiver ................................................. 167

Internal Voltage Regulator ....................................... 170

Interrupts ................................................................. 180

and USB Transactions ..................................... 180

Layered Framework ................................................. 189

Oscillator Requirements .......................................... 187

Output Enable Monitor ............................................. 169

Overview .......................................................... 165, 189

Ping-Pong Buffer Configuration ............................... 169

Power ...................................................................... 189

Power Modes ........................................................... 186

Bus Power Only ............................................... 186

Dual Power with Self-Power Dominance ......... 186

Self-Power Only ............................................... 186

RAM ......................................................................... 173

Memory Map .................................................... 173

Speed ...................................................................... 190

Status and Control ................................................... 166

Transfer Types ......................................................... 189

UFRMH:UFRML Registers ...................................... 173

USB. See Universal Serial Bus.

Voltage Reference Specifications .................................... 382

Watchdog Timer (WDT) ........................................... 291, 303

Associated Registers ............................................... 304

Control Register ....................................................... 303

During Oscillator Failure .......................................... 306

Programming Considerations .................................. 303

WCOL ...................................................... 230, 231, 232, 235

WCOL Status Flag ................................... 230, 231, 232, 235

WWW Address ................................................................ 433

WWW, On-Line Support ...................................................... 5

XORLW ............................................................................ 353

XORWF ........................................................................... 354

PIC18F4550ESOSQTP Datasheet(PDF) 434 Page - Microchip Technology

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