PSD833F2 datasheet(56/128 Pages) STMICROELECTRONICS

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14.9

Input macrocells (IMC)

The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The

architecture of the input macrocells (IMC) is shown in Figure 16. The input macrocells (IMC)

are individually configurable, and can be used as a latch, register, or to pass incoming port

signals prior to driving them onto the PLD input bus. The outputs of the input macrocells

(IMC) can be read by the MCU through the internal data bus.

The enable for the latch and clock for the register are driven by a multiplexer whose inputs

are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each

product term output is used to latch or clock four input macrocells (IMC). port inputs 3-0 can

be controlled by one product term and 7-4 by another.

Configurations for the input macrocells (IMC) are specified by equations written in PSDabel

(see Application Note AN1171). outputs of the input macrocells (IMC) can be read by the

MCU via the IMC buffer (see Section 16: I/O ports).

Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher

than A15. Any latched addresses are routed to the PLDs as inputs.

Input macrocells (IMC) are particularly useful with handshaking communication applications

where two processors pass data back and forth through a common mailbox. Figure 17

shows a typical configuration where the Master MCU writes to the port A Data Out register.

This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output

enable product term.

The Slave can also write to the port A input macrocells (IMC) and the Master can then read

the input macrocells (IMC) directly.

Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from

the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and

Slave_CS.

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PSD833F2 Datasheet(PDF) 56 Page - STMicroelectronics