PSD833F2 datasheet(76/128 Pages) STMICROELECTRONICS

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I/O ports

PSD8XXFX

76/128

Doc ID 7833 Rev 7

16.21

Port C – functionality and structure

Port C can be configured to perform one or more of the following functions (see Figure 28):

●

MCU I/O mode

●

CPLD Output – McellBC7-McellBC0 outputs can be connected to port B or port C.

●

CPLD input – via the input macrocells (IMC)

●

Address In – Additional high address inputs using the input macrocells (IMC).

●

In-system programming (ISP) – JTAG port can be enabled for programming/erase of

the PSD device (see Section 19: Programming in-circuit using the JTAG serial interface

for more information on JTAG programming).

●

Open Drain – port C pins can be configured in Open Drain mode

Port C does not support Address Out mode, and therefore no Control register is required.

Pin PC7 may be configured as the DBE input in certain MCU bus interfaces.

Figure 28.

Port C structure

16.22

Port D – functionality and structure

Port D has three I/O pins. See Figure 29 and Figure 30. This port does not support Address

Out mode, and therefore no Control register is required. port D can be configured to perform

one or more of the following functions:

●

MCU I/O mode

●

CPLD Output – External Chip Select (ECS0-ECS2)

●

CPLD input – direct input to the CPLD, no input macrocells (IMC)

●

Slew rate – pins can be set up for fast slew rate

DATA OUT

REG.

MCELLBC[ 7:0]

ENABLE PRODUCT TERM (.OE)

READ MUX

CPLD - INPUT

DIR REG.

INPUT

MACROCELL

ENABLE OUT

SPECIAL FUNCTION

CONFIGURATION

BIT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT C PIN

DATA OUT

AI02888B

Obsolete

Product(s)

- Obsolete

Product(s)

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