A43L0616AV datasheet(11/45 Pages) AMICC

11 / 45 page

A43L0616A

(May, 2001, Version 1.0)

AMIC Technology, Inc.

Mode Register Filed Table to Program Modes

Address

A10/AP

Function

RFU

W.B.L

CAS Latency

Burst Length

(Note 1)

(Note 2)

Test Mode

CAS Latency

Burst Type

Burst Length

Type

Latency

Type

BT=0

BT=1

Mode Register Set

Reserved

Sequential

Reserved

Interleave

Reserved

Vendor

Use

Only

Write Burst Length

Reserved

Length

Reserved

Burst

Reserved

Single Bit

Reserved

256(Full)

Reserved

(Note 3)

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200

µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256bit) is available only at Sequential mode of burst type.

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