A43L8316 datasheet(9/45 Pages) AMICC

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A43L8316

Preliminary (April, 2000, Version 1.0)

AMIC Technology, Inc.

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

CAS

Latency

-7

-8

-10

Unit

Note

tRRD(min)

Row active to row active delay

CLK

tRCD(min)

RAS

to CAS delay

CLK

tRP(min)

Row precharge time

CLK

tRAS(min)

CLK

tRAS(max)

Row active time

100

120

µs

tRC(min)

Row cycle time

CLK

tCDL(min)

Last data in new col. Address delay

CLK

tRDL(min)

Last data in row precharge

CLK

tBDL(min)

Last data in to burst stop

CLK

tCCD(min)

Col. Address to col. Address delay

CLK

Number of valid output data

CLK

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

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