A43L8316 datasheet(27/45 Pages) AMICC

Part #	A43L8316

Description	128K X 16 Bit X 2 Banks Synchronous DRAM

PDF	45 Pages

Scroll/Zoom	100%

Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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27 / 45 page

A43L8316

Preliminary (April, 2000, Version 1.0)

AMIC Technology, Inc.

Page Read & Write Cycle at Same Bank @Burst Length=4

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write

command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge

before end of burst. Input data after Row precharge cycle will be masked internally.

High

tRCD

CLOCK

CKE

RAS

CAS

ADDR

DQM

(CL=2)

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note 2

Ca0

Cb0

Cc0

A8/AP

Qa0

Qa1

Qb0

Qb1

Dc0

Dc1

Dd0

Dd1

Qa0

Qa1

Qb0

Write

(A-Bank)

Cd0

tRDL

tCDL

*Note 2

*Note1

*Note3

Dc0

Dc1

Dd0

Dd1

Read

(A-Bank)

Write

(A-Bank)

(CL=3)

A43L8316 Datasheet(PDF) 27 Page - AMIC Technology

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