PIC18F4550ESOSQTP datasheet(269/430 Pages) MICROCHIP

269 / 430 page

Preliminary

DS39632D-page 267

PIC18F2455/2550/4455/4550

21.6

A/D Conversions

Figure 21-4 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Figure 21-5 shows the operation of the A/D converter

after

the

GO/DONE

bit

has

been

set,

the

ACQT2:ACQT0 bits are set to ‘010’ and selecting a

4TAD acquisition time before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will NOT be updated with the partially completed

A/D

conversion

sample.

This

means

the

ADRESH:ADRESL registers will continue to contain

the value of the last completed conversion (or the last

value written to the ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can be

started. After this wait, acquisition on the selected

channel is automatically started.

21.7

Discharge

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged before

every sample. This feature helps to optimize the

unity-gain amplifier as the circuit always needs to

charge

the

capacitor

array,

rather

than

charge/discharge based on previous measurement

values.

FIGURE 21-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 21-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

On the following cycle:

TAD1

Discharge

Set GO/DONE bit

(Holding capacitor is disconnected)

Conversion starts

(Holding capacitor continues

acquiring input)

TACQ Cycles

TAD Cycles

Automatic

Acquisition

Time

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

TAD1

Discharge

PIC18F4550ESOSQTP Datasheet(PDF) 269 Page - Microchip Technology

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