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PIC18F4550ESOSQTP Datasheet(PDF) 270 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 270 Page - Microchip Technology |
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270 / 430 page  PIC18F2455/2550/4455/4550 DS39632D-page 268 Preliminary © 2007 Microchip Technology Inc. 21.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- grammed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automat- ically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input chan- nel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 SPPIF(4) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE(4) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP(4) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 ADRESH A/D Result Register High Byte 52 ADRESL A/D Result Register Low Byte 52 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 52 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 52 PORTA —RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 54 TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 54 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 54 PORTE RDPU(4) — — —RE3(1,3) RE2(4) RE1(4) RE0(4) 54 TRISE(4) — — — — — TRISE2 TRISE1 TRISE0 54 LATE(4) — — — — — LATE2 LATE1 LATE0 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: These registers and/or bits are not implemented on 28-pin devices. |
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