PIC18F4550ESOSQTP datasheet(294/430 Pages) MICROCHIP

294 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 292

Preliminary

CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)

R/P-1

R/P-0

U-0

R/P-1

U-0

R/P-1

DEBUG

XINST

ICPRT(1)

—

—LVP

—STVREN

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

bit 7

DEBUG: Background Debugger Enable bit

= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

bit 6

XINST: Extended Instruction Set Enable bit

= Instruction set extension and Indexed Addressing mode enabled

= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5

ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)

= ICPORT enabled

= ICPORT disabled

bit 4-3

Unimplemented: Read as ‘0’

bit 2

LVP: Single-Supply ICSP™ Enable bit

= Single-Supply ICSP enabled

= Single-Supply ICSP disabled

bit 1

Unimplemented: Read as ‘0’

bit 0

STVREN: Stack Full/Underflow Reset Enable bit

= Stack full/underflow will cause Reset

= Stack full/underflow will not cause Reset

Note 1:

Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all

other devices.

PIC18F4550ESOSQTP Datasheet(PDF) 294 Page - Microchip Technology

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