PIC18F4550ESOSQTP datasheet(305/430 Pages) MICROCHIP

305 / 430 page

Preliminary

DS39632D-page 303

PIC18F2455/2550/4455/4550

25.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn Configuration bit is ‘0’. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will

result

reading

‘0’s.

Figures 25-6 through 25-8

illustrate table write and table read protection.

FIGURE 25-6:

TABLE WRITE (WRTn) DISALLOWED

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

Chip Erase or Block Erase function. The

full Chip Erase and Block Erase functions

can only be initiated via ICSP operation or

an external programmer.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLWT*

TBLPTR = 0008FFh

PC = 001FFEh

TBLWT*

PC = 005FFEh

Program Memory

Configuration Bit Settings

Results: All table writes disabled to Blockn whenever WRTn = 0.

PIC18F4550ESOSQTP Datasheet(PDF) 305 Page - Microchip Technology

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