PIC18F4550ESOSQTP datasheet(189/430 Pages) MICROCHIP

189 / 430 page

Preliminary

DS39632D-page 187

PIC18F2455/2550/4455/4550

18.0

STREAMING PARALLEL PORT

PIC18F4455/4550 USB devices provide a Streaming

Parallel Port as a high-speed interface for moving data

to and from an external system. This parallel port

operates as a master port, complete with chip select

and clock outputs to control the movement of data to

slave devices. Data can be channelled either directly to

the USB SIE or to the microprocessor core. Figure 18-1

shows a block view of the SPP data path.

FIGURE 18-1:

SPP DATA PATH

In addition, the SPP can provide time multiplexed

addressing information along with the data by using the

second strobe output. Thus, the USB endpoint number

can be written in conjunction with the data for that

endpoint.

18.1

SPP Configuration

The operation of the SPP is controlled by two registers:

SPPCON and SPPCFG. The SPPCON register

(Register 18-1) controls the overall operation of the

parallel port and determines if it operates under USB or

microcontroller

control.

The

SPPCFG

(Register 18-2) controls timing configuration and pin

outputs.

18.1.1

ENABLING THE SPP

To enable the SPP, set the SPPEN bit (SPPCON<0>).

In addition, the TRIS bits for the corresponding SPP

pins must be properly configured. At a minimum:

• Bits TRISD<7:0> must be set (= 1)

• Bits TRISE<2:1> must be cleared (= 0)

If CK1SPP is to be used:

• Bit TRISE<0> must be cleared (= 0)

If CSPP is to be used:

• Bit TRISB<4> must be cleared (= 0)

Note:

The Streaming Parallel Port is only

available on 40/44-pin devices.

SPP

Logic

CK2SPP

OESPP

CSSPP

SPP<7:0>

CK1SPP

USB

CPU

PIC18F4455/4550

SIE

SPPCON: SPP CONTROL REGISTER

U-0

R/W-0

—

SPPOWN

SPPEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

Unimplemented: Read as ‘0’

bit 1

SPPOWN: SPP Ownership bit

= USB peripheral controls the SPP

= Microcontroller directly controls the SPP

bit 0

SPPEN: SPP Enable bit

= SPP is enabled

= SPP is disabled

PIC18F4550ESOSQTP Datasheet(PDF) 189 Page - Microchip Technology

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