PIC18F4550ESOSQTP datasheet(190/430 Pages) MICROCHIP

190 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 188

Preliminary

18.1.2

CLOCKING DATA

The SPP has four control outputs:

• Two separate clock outputs (CK1SPP and

CK2SPP)

• Output enable (OESPP)

• Chip select (CSSPP)

Together, they allow for several different configurations

for controlling the flow of data to slave devices. When

all control outputs are used, the three main options are:

• CLK1 clocks endpoint address information while

CLK2 clocks data

• CLK1 clocks write operations while CLK2 clocks

reads

• CLK1 clocks Odd address data while CLK2 clocks

Even address data

Additional control options are derived by disabling the

CK1SPP and CSSPP outputs. These are enabled or

disabled with the CLK1EN and CSEN bits, respectively,

located in Register 18-2.

18.1.3

WAIT STATES

The SPP is designed with the capability of adding wait

states to read and write operations. This allows access

to parallel devices that require extra time for access.

Wait state clocking is based on the data source clock.

If the SPP is configured to operate as a USB endpoint,

then wait states are based on the USB clock. Likewise,

if the SPP is configured to operate from the micro-

controller, then wait states are based on the instruction

rate (FOSC/4).

The WS3:WS0 bits set the wait states used by the SPP,

with a range of no wait states to 30 wait states, in multi-

ples of two. The wait states are added symmetrically to

all transactions, with one-half added following each of the

two clock cycles normally required for the transaction.

Figure 18-3 and Figure 18-4 show signalling examples

with 4 wait states added to each transaction.

18.1.4

SPP PULL-UPS

The SPP data lines (SPP<7:0>) are equipped with

internal pull-ups for applications that may leave the port

in a high-impedance condition. The pull-ups are

enabled using the control bit, RDPU (PORTE<7>).

SPPCFG: SPP CONFIGURATION REGISTER

R/W-0

CLKCFG1

CLKCFG0

CSEN

CLK1EN

WS3

WS2

WS1

WS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

CLKCFG1:CLKCFG0: SPP Clock Configuration bits

= CLK1 toggles on read or write of an Odd endpoint address;

CLK2 toggles on read or write of an Even endpoint address

= CLK1 toggles on write; CLK2 toggles on read

= CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write

bit 5

CSEN: SPP Chip Select Pin Enable bit

= RB4 pin is controlled by the SPP module and functions as SPP CS output

= RB4 functions as a digital I/O port

bit 4

CLK1EN: SPP CLK1 Pin Enable bit

= RE0 pin is controlled by the SPP module and functions as SPP CLK1 output

= RE0 functions as a digital I/O port

bit 3-0

WS3:WS0: SPP Wait States bits

1111

= 30 additional wait states

1110

= 28 additional wait states

•

0001

= 2 additional wait states

0000

= 0 additional wait states

PIC18F4550ESOSQTP Datasheet(PDF) 190 Page - Microchip Technology

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