AS3642 datasheet(7/27 Pages) AMSCO

7 / 27 page

www.austriamicrosystems.com/AS3642

1.2-2

6 - 26

AS3642

Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

Timing Diagrams

Figure 3. I

2C interface Timing Diagram

CI/O

I/O Capacitance

(SDA, SCL)

1. Limited to max. 5V due to overvoltage protection circuit on pin VOUT

2. Due to slope compensation of the current limit, ILIMIT changes with duty cycle - see Figure 16 on page 9.

3. Due to the architecture (the supply of the AS3642 is connected to the output VOUT), the undervoltage lockout

is only detected when the DCDC converter is not switching

4. The logic input levels VIH and VIL allow for 1.8V supplied driving circuit (70%/30% of 1.8V)

5. After this period, the first clock pulse is generated.

6. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

7. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then

be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max +

tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Table 3. Electrical Characteristics (Continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

SCL

SDA

tBUF

tHD:STA

tSU:STA

REPEATED

START

tSU:STO

tSU:DAT

tHIGH

tHD:DAT

tLOW

tHD:STA

START

STOP

AS3642 Datasheet(PDF) 7 Page - ams AG

AS3642 Datasheet(HTML) 7 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL