AT25DF641_13 datasheet(14/56 Pages) ETC2

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AT25DF641

3680F–DFLASH–4/10

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are

not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this

situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the

beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes

of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and

0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page

(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In

addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched

into the internal buffer.

When the

pin is deasserted, the device will take the data stored in the internal buffer and program it into the

appropriate memory array locations based on the starting address specified by A23-A0 and the number of data

bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within

the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is

internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.

The three address bytes and at least one complete byte of data must be clocked into the device before the

is deasserted, and the

pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the

device will abort the operation and no data will be programmed into the memory array. In addition, if the address

specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”

on page 22) or locked down (see “Sector Lockdown” on page 28), then the Byte/Page Program command will not

be executed, and the device will return to the idle state once the

pin has been deasserted. The WEL bit in the

Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address

being sent, an incomplete byte of data being sent, the

pin being deasserted on uneven byte boundaries, or

because the memory location to be programmed is protected or locked down.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For

faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to

determine if the data bytes have finished programming. At some point before the program cycle completes, the

WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to

program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

Figure 7-3.

Dual-Input Byte Program

SOI

SCK

MS B

10 11

31 32

29 30

OP C ODE

ADDR E S S B ITS A23-A0

MS B

INP UT

DATA B Y TE

HIG H-IMP E DANC E

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