AT25DF641_13 datasheet(26/56 Pages) ETC2

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AT25DF641

3680F–DFLASH–4/10

If the desire is to only change the SPRL bit without performing a G lobal Protect or Global Unprotect, then the

system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a

logical “0” provided the

pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from

a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the

Sector Protection Registers).

When writing to the first byte of the Status Register, bits five, four, three, and two will not actually be modified but

will be dec oded by the device for the purposes of the Global Protect and G lobal Unprotect functions. Only bit

seven, the SPRL bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits

five, four, three, and two will not reflect the values written to them but will instead indicate the status of the

and the sector protection status. Please refer to “Status Register Commands” on page 34 and Table 10-1 on page

34 for details on the Status Register format and what values can be read for bits five, four, three, and two.

8.6.

Read Sector Protection Registers

The Sector Protection Registers can be read to determine the current software protection status of each sector.

Reading the Sector Protection Registers, however, will not determine the status of the

pin.

To read the Sector Protection Register for a particular sector, the

pin must first be asserted and the opcode of

3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address

within the sector must be clocked in. After the last address byte has been clocked in, the device will begin

outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte

of either FFh or 00h to denote the value of the appropriate Sector Protection Register.

At clock frequencies above fCLK, the first byte of data output will not be v alid. Therefore, if operating at clock

frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the

correct status of the appropriate Sector Protection Register.

Table 8-3.

Read Sector Protection Register - Output Data

Output Data

Sector Protection Register Value

00h

Sector Protection Register value is 0 (sector is unprotected)

FFh

Sector Protection Register value is 1 (sector is protected)

Deasserting the

pin will terminate the read operation and put the SO pin into a high-impedance state. The

pin can be deasserted at any time and does not require that a full byte of data be read.

In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the

Status Register can be r ead to determine if all, some, or none of the sectors are software protected (refer to

“Read Status Register” on page 34 for more details).

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