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AT25DF641 Datasheet(PDF) 48 Page - List of Unclassifed Manufacturers |
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AT25DF641 Datasheet(HTML) 48 Page - List of Unclassifed Manufacturers |
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48 / 56 page ![]() 48 AT25DF641 3680F–DFLASH–4/10 13.4. AC Characteristics - Maximum Clock Frequencies Symbol Parameter Min Max Units RapidS and SPI Operation fMAX Maximum Clock Frequency for All Operations – RapidS Operation Only (excluding 0Bh, 03h, 3Bh, and 9F opcodes) 100 MHz fCLK Maximum Clock Frequency for All Operations (excluding 03h and 3Bh opcodes) 75 MHz fRDLF Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency) 45 MHz fRDDO Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read) 55 MHz 13.5. AC Characteristics – All Other Parameters Symbol Parameter Min Max Units tCLKH Clock High Time 4.3 ns tCLKL Clock Low Time 4.3 ns tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCSH Chip Select High Time 50 ns tCSLS Chip Select Low Setup Time (relative to Clock) 5 ns tCSLH Chip Select Low Hold Time (relative to Clock) 5 ns tCSHS Chip Select High Setup Time (relative to Clock) 5 ns tCSHH Chip Select High Hold Time (relative to Clock) 5 ns tDS Data In Setup Time 2 ns tDH Data In Hold Time 1 ns tDIS(1) Output Disable Time 5 ns tV(2) Output Valid Time 5 ns tOH Output Hold Time 2 ns tHLS Low Setup Time (relative to Clock) 5 ns tHLH Low Hold Time (relative to Clock) 5 ns tHHS High Setup Time (relative to Clock) 5 ns tHHH High Hold Time (relative to Clock) 5 ns tHLQZ(1) Low to Output High-Z 5 ns tHHQX(1) High to Output Low-Z 5 ns tWPS(1)(3) Write Protect Setup Time 20 ns tWPH(1)(3) Write Protect Hold Time 100 ns tSECP(1) Sector Protect Time (from Chip Select High) 20 ns tSECUP(1) Sector Unprotect Time (from Chip Select High) 20 ns tLOCK(1) Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High) 200 µ s tEDPD(1) Chip Select High to Deep Power-Down 1 µ s tRDPD(1) Chip Select High to Standby Mode 30 µ s tRST Reset Time 30 µ s Notes: 1. Not 100% tested (value guaranteed by design and characterization) 2. 15pF load at frequencies above 70MHz, 30pF otherwise 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1 HOLD HOLD HOLD HOLD HOLD HOLD |
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