DS80C320 datasheet(16/42 Pages) DALLAS

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DS80C320/DS80C323

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POWER MANAGEMENT

The DS80C320/DS80C323 provides the standard Idle and power-down (Stop) that are available on the

standard 80C32. However the device has enhancements that make these modes more useful, and allow

more power saving.

The Idle mode is invoked by setting the LSB of the Power Control register (PCON - 87h). Idle will leave

internal clocks, serial port and timer running. No memory access will be performed so power is

dramatically reduced. Since clocks are running, the Idle power consumption is related to crystal

frequency. It should be approximately ½ of the operational power. The CPU can exit the Idle state with

any interrupt or a reset.

The power-down or Stop mode is invoked by setting the PCON.1 bit. Stop mode is a lower power state

than Idle since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 µA

but is specified in the Electrical Specifications. The CPU will exit Stop mode from an external interrupt

or a reset condition.

Note that internally ge nerated interrupts (timer, serial port, watchdog) are not useful in Idle or Stop since

they require clocking activity.

IDLE MODE ENHANCEMENTS

A simple enhancement to Idle mode makes it substantially more useful. The innovation involves not the

Idle mode itself, but the watchdog timer. As mentioned above, the Watchdog Timer provides an optional

interrupt

capability.

This

interrupt

can

provide

periodic

interval

timer

bring

the

DS80C320/DS80C323 out of Idle mode. This can be useful even if the Watchdog is not normally used.

By enabling the Watchdog Timer and its interrupt prior to invoking Idle, a user can periodically come out

of Idle perform an operation, then return to Idle until the next operation. This will lower the overall power

consumption. When using the Watchdog Interrupt to cancel the Idle state, make sure to restart the

Watchdog Timer or it will cause a reset.

STOP MODE ENHANCEMENTS

The DS80C320/DS80C323 provides two enhancements to the Stop mode. As documented above, the

device provides a band-gap reference to determine Power- fail Interrupt and Reset thresholds. The default

state is that the band- gap reference is off when Stop mode is invoked. This allows the extremely low

power state mentioned above. A user can optionally choose to have the band-gap enabled during Stop

mode. This means that PFI and power- fail reset will be activated and are valid means for leaving Stop

mode.

In Stop mode with the band-gap on, ICC will be approximately 50 µA compared with 1 µA with the band-

gap off. If a user does not require a Power- fail Reset or Interrupt while in Stop mode, the band-gap can

remain turned off. Note that only the most power sensitive applications should turn off the band- gap, as

this results in an uncontrolled power down condition.

The control of the band- gap reference is located in the Extended Interrupt Flag register (EXIF - 91h).

Setting BGS (EXIF.0) to a 1 will leave the band-gap reference enabled during Stop mode. The default or

reset condition is with the bit at a logic 0. This results in the band-gap being turned off during Stop mode.

Note that this bit has no control of the reference during full power or Idle modes.

DS80C320 Datasheet(PDF) 16 Page - Dallas Semiconductor

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