ADC12D040

SNAS171D – MAY 2004 – REVISED DECEMBER 2005

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The INT/EXT REF Pin

The INT/EXT REF pin determines whether the internal reference or an external reference voltage is used. With

this pin at a logic low, the internal 2.0V reference is in use. With this pin at a logic high an external reference

pin when the internal reference is used. There is no access to the internal reference voltage, but its value is

DATA OUTPUT PINS

The ADC12D040 has 24 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while

change of clock frequency. At the rated 40 MHz clock rate, the data transition is about 6 to 10 ns after the rise of

used to capture data, depending upon the data setup time of the circuit accepting the data. Also, circuit board

layout will affect relative delays of the clock and data, so it is important to consider these relative delays when

designing the digital interface. At sample frequencies below 40 MHz, there is a longer time between data

transition and the fall of the clock, so that the falling edge of the clock is generally the best edge to use for output

data capture at low sample rates.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series resistors of about 100

Ω at the digital

outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the

output currents, which could otherwise result in performance degradation. See Figure 5.

Note that, although the ADC12D040 has Tri-State outputs, these outputs should not be used to drive a bus and

the charging and discharging of large capacitances can degrade SNR performance. Each output pin should drive

only one pin of a receiving device and the interconnecting lines should be as short as practical.

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series

inductance.

As is the case with all high-speed converters, the ADC12D040 is sensitive to power supply noise. Accordingly,

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during turn on and turn off of power.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12D040 between these areas, is required to achieve

specified performance.

The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12D040's other ground pins.

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