ADC12D040

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SNAS171D – MAY 2004 – REVISED DECEMBER 2005

ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference

Check for Samples: ADC12D040

1

FEATURES

APPLICATIONS

23

•

Binary or 2’s complement output format

•

Ultrasound and Imaging

•

Single supply operation

•

Instrumentation

•

Internal sample-and-hold

•

Communications Receivers

•

Outputs 2.4V to 5V compatible

•

Sonar/Radar

•

Power down mode

•

xDSL

•

Pin-compatible with ADC12DL066

•

Cable Modems

•

Internal/External Reference

DESCRIPTION

The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog

input signals into 12-bit digital words at 40 Megasamples per second (Msps), minimum. This converter uses a

differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize

die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power

supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 mW at 40 Msps,

including the reference current. The Power Down feature reduces power consumption to 75 mW.

ended input. Full use of the differential input is recommended for optimum performance. The digital outputs for

the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2’s

complement.

For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate

supply voltage in the range of 2.4V to the digital supply voltage, making the outputs compatible with low voltage

systems. The ADC12D040’s speed, resolution and single supply operation make it well suited for a variety of

applications.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of

−40°C to +85°C. An evaluation board is available to facilitate the product evaluation process

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. Key Specifications

VALUE

UNIT

68

dB (typ)

10.9

bits (typ)

80

dB (typ)

Data Latency

6 Clock Cycles

Supply Voltage

+5V ±5%

Operating

600

mW (typ)

Power Consumption, Operating

Power Down

75

mW (typ)

Mode

1

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

TRI-STATE is a registered trademark of National Semiconductor Corporation.

3

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PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.