ADC12D040CIVSSLASHNOPB datasheet(9/31 Pages) TI1

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conversions.

ADC12D040

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SNAS171D – MAY 2004 – REVISED DECEMBER 2005

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =

+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits

apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3)

Typical

Limits

Units

Symbol

Parameter

Conditions

(4)

(Limits)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

VIN(1)

Logical “1” Input Voltage

VD = 5.25V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 4.75V

1.0

V (max)

IIN(1)

Logical “1” Input Current

VIN = 5.0V

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

VDR = 2.5V

2.3

V (min)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA

VDR = 3V

2.7

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA, VDR = 3V

0.4

V (max)

VOUT = 2.5V or 5V

100

IOZ

TRI-STATE Output Current

VOUT = 0V

−100

+ISC

Output Short Circuit Source Current

VOUT = 0V

−20

−ISC

Output Short Circuit Sink Current

VOUT = VDR

COUT

Digital Output Capacitance

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, VREF = 2.0V

110

mA (max)

Analog Supply Current

PD Pin = VDR

PD Pin = DGND

mA (max)

Digital Supply Current

PD Pin = VDR

PD Pin = DGND, CL = 0 pF

(5)

10.5

mA (max)

IDR

Digital Output Supply Current

PD Pin = VDR

PD Pin = DGND, CL = 0 pF

(6)

600

700

Total Power Consumption

PD Pin = VDR

Rejection of Full-Scale Error with

PSRR1

Power Supply Rejection

VA = 4.75V vs. 5.25V

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per (). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100

mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate

(2)

To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL

(Average Outgoing Quality Level).

(5)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x

f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

(6)

Excludes IDR. See note 14.

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