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LP3943 Datasheet(PDF) 7 Page - Texas Instruments |
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LP3943 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 21 page ![]() -40 80 TEMPERATURE (°C) -10 -5 0 5 10 60 40 20 0 -20 LP3943 www.ti.com SNVS256A – MAY 2004 – REVISED MAY 2004 Electrical Characteristics (continued) Unless otherwise noted, VDD = 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40°C to +125°C. (1) Limit Symbol Parameter Conditions Typical Units Min Max tTRANS Maximum Pulse Width of Spikes (3) that Must Be Suppressed by the 50 ns Input Filter of Both DATA & CLK Signals Typical Performance Characteristics Frequency vs. Temp (TA = −40°C to +85°C), VDD = 2.3V to 3.0V Application Notes THEORY OF OPERATION The LP3943 takes incoming data from the baseband controller and feeds them into several registers that control the frequency and the duty cycle of the LEDs. Two prescaler registers and two PWM registers provide two individual rates to dim or blink the LEDs (for more information on these registers, refer to Table 3). Each LED can be programmed in one of four states—on, off, DIM0 rate or DIM1 rate. Two read-only registers provide status on all 16 LEDs. The LP3943 can be used to drive RGB LEDs and/or single-color LEDs to create a colorful, entertaining, and informative setting. Alternatively, it can also drive RGB LED as a flashlight. This is particularly suitable for accessory functions in cellular phones and toys. Any LED pins not used to drive LED can be used for General Purpose Parallel Input/Output (GPIO) expansion. The LP3943 is equipped with Power-On Reset that holds the chip in a reset state until VDD reaches VPOR during power up. Once VPOR is achieved, the LP3943 comes out of reset and initializes itself to the default state. To bring the LP3943 into reset, hold the RST pin LOW for a period of TW. This will put the chip into its default state. The LP3943 can only be programmed after RST signal is HIGH again. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. Copyright © 2004, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LP3943 |
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