LP3943 datasheet(8/21 Pages) TI1

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LP3943

SNVS256A – MAY 2004 – REVISED MAY 2004

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Figure 3. I2C Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 4. I2C START and STOP Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first.

The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by

an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the

9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an

acknowledge after each byte has been received.

After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by

an eighth bit which is a data direction bit (R/W). The LP3943 hardwires bits 7 to 4 and leaves bits 3 to 1

selectable, as shown in Figure 5. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The

LP3943 supports only a WRITE during chip addressing. The second byte selects the register to which the data

will be written. The third byte contains data to write to the selected register.

Figure 5. Chip Address Byte

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