82091AA datasheet(41/204 Pages) INTEL

41 / 204 page

82091AA

290486 – 12

Figure 12 Parallel Port Power Management and Status Register

Bit

Description

RESERVED

PARALLEL PORT FIFO ERROR STATUS (PFERR)

When PFERRe1 a FIFO underrun or overrun

condition has occurred This bit is read only Setting PRESET to 1 clears this bit to 0

RESERVED

PARALLEL PORT AUTO POWERDOWN ENABLE (PAPDN)

When PAPDNe1 the parallel port

can enter auto powerdown if the required auto powerdown conditions are met When PAPDNe0

auto powerdown is disabled

PARALLEL PORT RESET (PRESET)

When PRESET is set to 1 the parallel port is reset (ie all

programming and current state information is lost) This is the same state the module would be in

after a hard reset (RSTDRV asserted) to the 82091AA When resetting the parallel port via this

configuration bit the software must toggle this bit and ensure the reset active time (PRESETe1) of

113 ms minimum is met

PARALLEL PORT IDLE STATUS (PIDLE)

This bit reflects the idle state of the parallel port When

the parallel port is in an idle state (ie when the same conditions are met that apply to entering auto

powerdown) the 82091AA sets this bit to 1 The parallel port idle state is defined as the FIFO empty

and no activity on the parallel port interface This bit is read only

PARALLEL PORT DIRECT POWERDOWN (PDPDN)

When PDPDN is set to 1 the parallel port

enters direct powerdown When PDPDN is set to 0 the parallel port is not in direct powerdown Note

that a parallel port module reset (PRESET bit in this register) also brings the parallel port out of the

direct powerdown state

82091AA Datasheet(PDF) 41 Page - Intel Corporation