8X930AX datasheet(13/38 Pages) INTEL

13 / 38 page

ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

T2EX

Timer 2 External Input. In timer 2 capture mode, a falling

edge initiates a capture of the timer 2 registers. In auto-

reload mode, a falling edge causes the timer 2 registers to

be reloaded. In the up-down counter mode, this signal

determines the count direction: 1 = up, 0 = down.

P1.1

TXD

Transmit Serial Data. TXD outputs the shift clock in serial

I/O mode 0 and transmits serial data in serial I/O modes 1,

2, and 3.

P3.1

PWR

Supply Voltage. Connect this pin to the +5V supply volt-

age.

—

CCP

PWR

Supply Voltage for I/O buffers. Connect this pin to the

+5V supply voltage.

—

GND

Circuit Ground. Connect this pin to ground.

—

SSP

GND

Circuit Ground for I/O buffers. Connect this pin to ground.

—

WAIT#

Real-time Wait State Input. The real-time WAIT# input is

enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit

at S:A7H. During bus cycles, the external memory system

can signal ‘system ready’ to the microcontroller in real time

by controlling the WAIT# input signal on the port 1.6 input.

P1.6/CEX3

WCLK

Wait Clock Output. The real-time WCLK output is driven at

port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1

(RTWCE) bit at S:A7H. When enabled, the WCLK output

produces a square wave signal with a period of T

CLK.

P1.7/CEX4/A17

WR#

Write. Write signal output to external memory.

P3.6

XTAL1

Input to the On-chip, Inverting, Oscillator Amplifier. To

use the internal oscillator, a crystal/resonator circuit is con-

nected to this pin. If an external oscillator is used, its output

is connected to this pin. XTAL1 is the clock source for inter-

nal timing.

—

XTAL2

Output of the On-chip, Inverting, Oscillator Amplifier. To

use the internal oscillator, a crystal/resonator circuit is con-

nected to this pin. If an external oscillator is used, leave

XTAL2 unconnected.

—

Table 5. Signal Descriptions (Continued)

Signal

Name

Type

Description

Alternate Function

† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the

chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-

ries the upper address bits (A15:8) and the data (D7:0).

8X930AX Datasheet(PDF) 13 Page - Intel Corporation

8X930AX Datasheet(HTML) 13 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL