8X930AX datasheet(35/38 Pages) INTEL

35 / 38 page

ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

8.0

SPECIFICATION SUPPLEMENT

FOR 8

X930AX3 AND 8X930AX4

All descriptions above apply to the 8

x930Ax and

x930Ax2 microcontrollers. The following specifica-

tions apply to recent steppings of the 8

x930Ax

x930Ax3 and 8x930Ax4). This information is in

addition to (or in place of) the specifications

described above.

8.1

Six Endpoint Pairs Functionality

the

default

state,

the

SIXEPPEN

bit

x930Ax3’s and 8x930Ax4’s EPCONFIG SFR is

cleared and the 6 endpoint pair feature is disabled.

In this state, the endpoint pairs of the 8

x930Ax3 and

x930Ax4 are similar to those of the 8x930Ax and

x930Ax2 devices.

enable

the

endpoint

pair

feature,

set

EPCONFIG’s SIXEPPEN bit. The 8

x930Ax3 and

x930Ax4 will then have the endpoint pairs shown

in Table 17.

When the 6 endpoint pair feature is enabled, two

additional SFRs — the Function Interrupt Enable

interrupts for the additional endpoint pairs.

See the

8x930Ax, 8x930Hx Universal Serial Bus

Microcontroller User’s Manual for additional infor-

mation.

8.2

DC Characteristics

The V

OH specification given in the DC Character-

istics section of this datasheet is changed to V

OH =

{min} V

CC – 1.7 V when IOH = -60 µA for the A3

stepping onward.

8.3

Extended Data Float (EDF) AC

Timing Feature

To provide a direct interface capability to slower

memory without the use of tristate drivers, an

extended data float (EDF) option has been added to

the 8

x930Ax3 and 8x930Ax4. This option is

controlled by the EDF# bit (bit 3 in the UCONFIG1

configuration byte).

If the EDF# bit is configured to 1, the 8

x930Ax3 and

x930Ax4 behave per the current specification

(some AC timings are different). This is known as

"Compatibility Mode". Table 19 on page 32 lists the

AC characteristics in this "Compatibility Mode" that

are

different

compared

the

8x930Ax

and

8x930Ax2. Parameters not listed in the table remain

the same as for 8

x930Ax and 8x930Ax2.

If the 8

x930Ax3 and 8x930Ax4 are configured with

EDF# = 0, the device will have extended data float

timings. This mode is known as the “Increased

RHDZ

1 Mode.” Table 20 on page 32 and Table 21

on page 33 show the parameters that are affected

when EDF#= 0.

Configuring the device with EDF# = 0 does not

affect wait state A (all regions except 01:). Wait

state A can have 0, 1, 2, or 3 wait states. EDF#=0

affects external wait state B (region 01:). The

summary of the effect EDF# has on wait states is

listed in Table 18.

Table 17. SIx Endpoint Pair Feature

EPINDEX

FFSZ1:0

Transmit

FIFO

(bytes)

Receive

FIFO

(bytes)

0xxx x000

0xxx x001

256

0xxx x010

0xxx x011

0xxx x100

0xxx x101

Table 18. Effect of “EDF#” on Wait States

EDF#

WSB#[1:0]

Wait-state

(for page 01)

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