ADE7758_15 datasheet(56/72 Pages) AD

56 / 72 page

ADE7758

Data Sheet

Rev. E | Page 56 of 72

in the interrupt status register are set irrespective of the state of

the mask bits. To determine the source of the interrupt, the

MCU should perform a read from the reset interrupt status

RSTATUS, Address 0x1A. The IRQ output goes logic high on

completion of the interrupt status register read command (see

the

section). When carrying out a read with

reset, the

is designed to ensure that no interrupt

events are missed. If an interrupt event occurs just as the

interrupt status register is being read, the event is not lost, and

the

Interrupt Timing

ADE7758

IRQ logic output is guaranteed to go logic high for the

duration of the interrupt status register data transfer before

going logic low again to indicate the pending interrupt. Note

that the reset interrupt bit in the status register is high for only

one clock cycle, and it then goes back to 0.

USING THE INTERRUPTS WITH AN MCU

Figure 87 shows a timing diagram that illustrates a suggested

implementation of ADE7758 interrupt management using an

MCU. At time t1, the IRQ line goes active low indicating that

one or more interrupt events have occurred in the

The

ADE7758

IRQ logic output should be tied to a negative-edge-

triggered external interrupt on the MCU. On detection of the

negative edge, the MCU should be configured to start executing

its interrupt service routine (ISR). On entering the ISR, all

interrupts should be disabled using the global interrupt mask

bit. At this point, the MCU external interrupt flag can be

cleared to capture interrupt events that occur during the current

ISR. When the MCU interrupt flag is cleared, a read from the

reset interrupt status register with reset is carried out. (This

causes the IRQ line to be reset logic high (t2); see the

section.) The reset interrupt status register contents are

used to determine the source of the interrupt(s) and hence the

appropriate action to be taken. If a subsequent interrupt event

occurs during the ISR (t3) that event is recorded by the MCU

external interrupt flag being set again.

Interrupt

Timing

On returning from the ISR, the global interrupt mask bit is

cleared (same instruction cycle) and the external interrupt flag

uses the MCU to jump to its ISR once again. This ensures that

the MCU does not miss any external interrupts. The reset bit in

the status register is an exception to this and is only high for one

clock cycle after a reset event.

INTERRUPT TIMING

The Serial Interface section should be reviewed before

reviewing this section. As previously described, when the IRQ

output goes low, the MCU ISR must read the interrupt status

the interrupt status register contents, the IRQ output is set high

on the last falling edge of SCLK of the first byte transfer (read

interrupt status register command). The IRQ output is held

high until the last bit of the next 8-bit transfer is shifted out

(interrupt status register contents), as shown in

. If an

interrupt is pending at this time, the

Figure 88

IRQ output goes low again.

If no interrupt is pending, the IRQ output remains high.

SERIAL INTERFACE

The ADE7758 has a built-in SPI interface. The serial interface

of the ADE7758 is made of four signals: SCLK, DIN, DOUT,

and CS. The serial clock for a data transfer is applied at the

SCLK logic input. This logic input has a Schmitt trigger input

structure that allows slow rising (and falling) clock edges to be

used. All data transfer operations are synchronized to the serial

clock. Data is shifted into the

at the DIN logic input

on the falling edge of SCLK. Data is shifted out of the

at the DOUT logic output on a rising edge of SCLK.

ADE7758

The CS logic input is the chip select input. This input is used

when multiple devices share the serial bus. A falling edge on CS

also resets the serial interface and places the

communications mode.

ADE7758

The CS input should be driven low for the entire data transfer

operation. Bringing CS high during a data transfer operation

aborts the transfer and places the serial bus in a high impedance

state. The CS logic input can be tied low if the

is the

only device on the serial bus.

ADE7758

However, with CS tied low, all initiated data transfer operations

must be fully completed. The LSB of each register must be

transferred because there is no other way of bringing the

back into communications mode without resetting

the entire device, that is, performing a software reset using Bit 6

of the OPMODE[7:0] register, Address 0x13.

ADE7758

The functionality of the ADE7758 is accessible via several on-

chip registers (see Figure 89). The contents of these registers can

be updated or read using the on-chip serial interface. After a

falling edge on CS, the

is placed in communications

mode. In communications mode, the

expects the first

communication to be a write to the internal communications

contains the address and specifies the next data transfer to be a

read or a write command. Therefore, all data transfer operations

with the

, whether a read or a write, must begin with a

write to the communications register.

ADE7758

ADE7758 Datasheet(PDF) 56 Page - Analog Devices

ADE7758 Datasheet(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL